/*
 * (C) Copyright 2010
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _LOONGSON_ETH_GMAC_H
#define _LOONGSON_ETH_GMAC_H

#define CONFIG_TX_DESCR_NUM	16
#define CONFIG_RX_DESCR_NUM	16

#define ETHERNET_HEADER             14	 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type
#define ETHERNET_CRC                 4	 //Ethernet CRC
#define VLAN_TAG		                4  //optional 802.1q VLAN Tag
#define MIN_ETHERNET_PAYLOAD        46  //Minimum Ethernet payload size
#define MAX_ETHERNET_PAYLOAD      1500  //Maximum Ethernet payload size
//#define CONFIG_ETH_BUFSIZE	ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG
#define CONFIG_ETH_BUFSIZE	1984
#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE)
#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE)

#define CONFIG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)

struct eth_mac_regs {
	u32 conf;		/* 0x00 */
	u32 framefilt;		/* 0x04 */
	u32 hashtablehigh;	/* 0x08 */
	u32 hashtablelow;	/* 0x0c */
	u32 miiaddr;		/* 0x10 */
	u32 miidata;		/* 0x14 */
	u32 flowcontrol;	/* 0x18 */
	u32 vlantag;		/* 0x1c */
	u32 version;		/* 0x20 */
	u8 reserved_1[20];
	u32 intreg;		/* 0x38 */
	u32 intmask;		/* 0x3c */
	u32 macaddr0hi;		/* 0x40 */
	u32 macaddr0lo;		/* 0x44 */
};

/* MAC configuration register definitions */
#define WD_DISABLE	(1 << 23)
#define JD_DISABLE	(1 << 22)
#define FRAMEBURSTENABLE	(1 << 21)
#define JE_ENABLE	(1 << 20)
#define MII_PORTSELECT		(1 << 15)
#define FES_100			(1 << 14)
#define DISABLERXOWN		(1 << 13)
#define LOOPBACKMODE		(1 << 12)
#define FULLDPLXMODE		(1 << 11)
#define DISABLE_RETRY	(1 << 9)
#define PADCRCSTRIP	(1 << 7)
#define RXENABLE		(1 << 2)
#define TXENABLE		(1 << 3)

/* MII address register definitions */
#define MII_BUSY		(1 << 0)
#define MII_WRITE		(1 << 1)
#define MII_CLKRANGE_60_100M	(0)
#define MII_CLKRANGE_100_150M	(0x4)
#define MII_CLKRANGE_20_35M	(0x8)
#define MII_CLKRANGE_35_60M	(0xC)
#define MII_CLKRANGE_150_250M	(0x10)
#define MII_CLKRANGE_250_300M	(0x14)

#define MIIADDRSHIFT		(11)
#define MIIREGSHIFT		(6)
#define MII_REGMSK		(0x1F << 6)
#define MII_ADDRMSK		(0x1F << 11)


struct eth_dma_regs {
	u32 busmode;		/* 0x00 */
	u32 txpolldemand;	/* 0x04 */
	u32 rxpolldemand;	/* 0x08 */
	u32 rxdesclistaddr;	/* 0x0c */
	u32 txdesclistaddr;	/* 0x10 */
	u32 status;		/* 0x14 */
	u32 opmode;		/* 0x18 */
	u32 intenable;		/* 0x1c */
	u32 reserved1[2];
	u32 axibus;		/* 0x28 */
	u32 reserved2[7];
	u32 currhosttxdesc;	/* 0x48 */
	u32 currhostrxdesc;	/* 0x4c */
	u32 currhosttxbuffaddr;	/* 0x50 */
	u32 currhostrxbuffaddr;	/* 0x54 */
};

#define DW_DMA_BASE_OFFSET	(0x1000)

/* Default DMA Burst length */
#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
#endif

/* Bus mode register definitions */
#define PBL8X_MODE		(1 << 24)
#define FIXEDBURST		(1 << 16)
#define PRIORXTX_41		(3 << 14)
#define PRIORXTX_31		(2 << 14)
#define PRIORXTX_21		(1 << 14)
#define PRIORXTX_11		(0 << 14)
#define DMA_PBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
#define DMA_RPBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<17)
#define RXHIGHPRIO		(1 << 1)
#define DMAMAC_SRST		(1 << 0)

/* Poll demand definitions */
#define POLL_DATA		(0xFFFFFFFF)

/* Operation mode definitions */
#define STOREFORWARD		(1 << 21)
#define FLUSHTXFIFO		(1 << 20)
#define TXSTART			(1 << 13)
#define TXSECONDFRAME		(1 << 2)
#define RXSTART			(1 << 1)

/* Descriptior related definitions */
#define MAC_MAX_FRAME_SZ	(1600)

struct dmamacdescr
{
	u32   status;         /* Status 									*/
	u32   length;         /* Buffer 1  and Buffer 2 length 						*/
	u32   buffer1;        /* Network Buffer 1 pointer (Dma-able) 							*/
	u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure 	*/
// This data below is used only by driver
	u32   data1;          /* This holds virtual address of buffer1, not used by DMA  			*/
	u32   data2;          /* This holds virtual address of buffer2, not used by DMA  			*/
// for addr align
	u32 	dummy1;
	u32   dummy2;
};

struct dwdmadev
{
	struct dmamacdescr *TxDesc;               /* start address of TX descriptors ring or chain, this is used by the driver  */
	struct dmamacdescr *RxDesc;               /* start address of RX descriptors ring or chain, this is used by the driver  */

	u32  RxDescCount;              /* number of rx descriptors in the tx descriptor queue/pool */
	u32  TxDescCount;              /* number of tx descriptors in the rx descriptor queue/pool */

	u32  TxBusy;                   /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr()                */
	u32  TxNext;                   /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
	u32  RxBusy;                   /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr()                   */
	u32  RxNext;                   /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */

	struct dmamacdescr *TxBusyDesc;          /* Tx Descriptor address corresponding to the index TxBusy */
	struct dmamacdescr *TxNextDesc;          /* Tx Descriptor address corresponding to the index TxNext */
	struct dmamacdescr *RxBusyDesc;          /* Rx Descriptor address corresponding to the index TxBusy */
	struct dmamacdescr *RxNextDesc;          /* Rx Descriptor address corresponding to the index RxNext */

	u32 free_pkt;
};

struct dw_eth_dev {
	struct dwdmadev *dmadev;

	u32 interface;
	u32 tx_currdescnum;
	u32 rx_currdescnum;

	struct eth_mac_regs *mac_regs_p;
	struct eth_dma_regs *dma_regs_p;

	struct eth_device *dev;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

#endif
